1. Field of the Invention
This invention relates to an integrated circuit containing a scan circuit in which sequential circuits such as flip-flops are connected in the form of a shift register in order to facilitate the test during the manufacture.
2. Description of the Related Art
In the manufacture of an integrated circuit using a gate array, etc., it is required to conduct a test for determining whether or not a manufactured chip normally functions. However, the test pattern (inspection series) for an integrated circuit including sequential circuits (elements having memory functions) such as flip-flops and latches is complex and huge. Therefore, a scan pass method has been practically used in which the internal state is set and read out by switching sequential circuits to connect them in the form of a shift register and applying a scan clock signal only to these circuits. According to this method, it is easy to prepare a test pattern.
FIG. 1 is a diagram showing one portion of an integrated circuit using the scan pass method. In the figure, three flip-flops are shown in which the memory state is set and read out by a scan clock signal. Each of the flip-flops 60 includes a flip-flop main body 61 which is a D-type flip-flop, a data selector 62, and a clock selector 63. As is well known, a D-type flip-flop is a flip-flop which outputs from the Q output terminal the state of the data input terminal D at the time when a clock signal (rising edge) is input. The data selector 62 is a switch circuit by which the connection of the D terminal of the flip-flop main body 61 is switched to the data input terminal 64 in the primary operation (normal operation) of the integrated circuit, or to the scan-in terminal 65 for receiving the input from a flip-flop which is connected in the preceding stage in the read out operation (scan operation) wherein the flip-flops are connected during the test process in the form of a shift register to read out the memory contents. The clock selector 63 is a switch circuit which selects one of the system clock signal and the scan clock signal and supplies the selected clock signal to the clock (CK) terminal of the flip-flop main body 61. The switch operations of the data selector 62 and clock selector 63 are controlled by the same select signal from an LSI tester.
The system clock signal is a clock signal used in the normal operation, and applied to all circuits of the integrated circuit. Depending upon the configuration of the integrated circuit, there may be a case that the same clock signal is not applied to all circuits of the integrated circuit. Today, with the increased scale of integrated circuits, it has been popular that a plurality of system clock signals exit in an integrated circuit of one chip. On the other hand, the scan clock signal is a clock signal which is applied only to sequential circuits from which data must be read out during the test process as illustrated, and the same scan clock signal is applied to all circuits which are connected in the form of a shift register.
In a conventional integrated circuit such as shown in FIG. 1, all of the flip-flops which are to be connected in the form of a shift register are provided with the data selector 62 and the clock selector 63. These selectors may have a configuration such as shown in FIG. 3(A). When this configuration is realized by basic cells of a gate array, it is required to use three gates. Although only three flip-flops are shown in FIG. 1, the number of flip-flops which are subjected to the scan path method (or connected in the form of a shift register) in an actual integrated circuit amounts from several tens to several hundreds. When the selectors are provided for all of these flip-flops, a very large number of gates are required for performing the selection of clock signals, thereby developing a defect that the circuit configuration becomes large.